1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a semiconductor memory device comprising a pseudo ground pad and a method of making the semiconductor memory device comprising the pseudo ground pad.
This application claims priority to Korean Patent Application No. 2005-86449, filed Sep. 15, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Increased sophistication and specialization within the fabrication and provision of semiconductor devices, as well as increased diversity in the manner by which semiconductor devices are incorporated within various host devices have resulted in new demands upon the testing capabilities of the constituent semiconductor devices. Where once a great majority of semiconductor devices were powered for testing only after being incorporated into a package, many contemporary semiconductor devices must first be tested at the wafer level (i.e., before being cut from a wafer substrate). That is, an increased demand for wafer level testing necessitates changes in the test-related design and operation of semiconductor devices.
For example, one common test applied to semiconductor devices measures certain parasitic influences between circuit elements of the semiconductor device. While such parasitic influences are often distributed in nature, they are routinely modeled and/or expressed in terms of discrete parasitic elements. In one sense, these discrete parasitic elements may be viewed as “virtual” elements of the various circuits formed on a semiconductor device.
Such parasitic elements include parasitic capacitances C and parasitic resistances R that are commonly formed between adjacent signal (e.g., power, data, address, and/or control) lines. Such signal lines may be formed on the same or different material layers of a multi-layer semiconductor device. Parasitic capacitance and resistance elements are routinely present in coincidence and may be modeled as parasitic RC elements. In several effects, parasitic RC elements cause signal line propagation delays, increase the power consumption, and increase current leakage. Parasitic elements may be determined by calculating a reflective characteristic S11 of a data pad and a transfer characteristic S21 of a pair of differential data pads.
In accordance with a conventional method of measuring parasitic elements of a first data pad, a test device connects a probe tip to the first data pad and a corresponding ground voltage pad to calculate reflection characteristic S11 of the first data pad. Also, the test device uses a first probe tip of a pair of probe tips to connect a primary data pad to a corresponding ground voltage pad and uses a second probe tip of the pair of probe tips to connect a secondary data pad to a corresponding ground voltage pad, wherein the primary and secondary data pads are differential data pads (and one of the primary and secondary data pads is the first data pad), to calculate transfer characteristic S21 of the data pad.
The shape and size of the probe tip of the test device is fixed, so a data pad and a ground voltage pad can only be connected using a single probe tip when the data pad and the ground voltage pad are adjacent to one another in a semiconductor memory device.
However, in a conventional semiconductor memory device, a plurality of pads is arranged in a central region of the semiconductor memory device as shown in FIG. (FIG.) 1. In the conventional semiconductor memory device, pluralities of data pads, power supply voltage pads, and ground voltage pads are arranged to form lines, and in that arrangement not every data pad is adjacent to a ground voltage pad.
In other words, since less than all of the data pads are adjacent to a ground voltage pad, less than all of the data pads can be connected to the test device to calculate reflection characteristic S11 using the probe tip. In addition, the probability of having a pair of differential data pads wherein each data pad of the pair is adjacent to a ground voltage pad is also low, so the probability of being able to measure transfer characteristic S21 of a data pad using the test device connected to a pair of differential data pads and corresponding ground voltage pads is also low. That is, it is difficult to find data pads that can be used to measure transfer characteristic S21 in the conventional semiconductor-memory device.
Consequently, when a semiconductor memory device has a structure in which a plurality of pads are arranged in lines as shown in FIG. 1, the reflection characteristic cannot be measured for every data pad using the test device, and there are few data pads for which the transfer characteristic can be measured. Accordingly, the parasitic influences (i.e., the total of the parasitic elements) of the semiconductor memory device must be inferred from the reflection characteristic of a limited number of data pads, so the conventional semiconductor memory device cannot be reliably analyzed.